The present invention relates generally to apparatuses and methods for protecting solar cells and, more specifically to apparatuses and methods for protecting a solar cell from electrostatic discharge damage (ESD).
The interest in photovoltaic (PV) cells continues as concerns over pollution and limited resources continue. The continued interest has been in both terrestrial and non-terrestrial applications. In the non-terrestrial environment of outer space, the concern over limited resources of any type is a major one. This is because the need to increase the amount of a resource increases the weight. An increased weight can increase the cost of a launch more than linearly. With the ready availability of solar energy in outer space for a spacecraft, the conversion of solar energy into electrical energy has become a standard method of powering a spacecraft. Irrespective of the application, and as with any energy generation system, efforts have been ongoing into increasing the output and/or efficiency. One such effort has been the adoption use of multi-junction PV cells, such as triple junction GaAs cells, which convert sunlight to power with higher efficiency.
A problem with solar cells is the degradation and damage caused by reverse bias operation. Whenever solar cells are connected in a series array, shadowed or cracked solar cells may be subjected to reversed bias voltage and current. Cells that are operated in reverse bias may be permanently degraded by as little as a few percent in performance up to complete short-circuit failure [Rauschenbach, Solar Cell Array Design Handbook, 1980, Chapter 4–25]. It has become standard practice in solar array design to provide bypass diodes (also called shunt diodes) to protect cells from reverse bias degradation [Rauschenbach, chapter 6–27], and to perform reverse bias screening tests to weed out solar cells that could still degrade even with bypass diodes [see for example, Rosenberg and Gasner, “Reverse-Bias Screening of Large-Area GaAs/Ge Solar Cells at Low and High Temperatures”, 23rd IEEE Photovoltaic Specialists Conference, 1993, pp 1421–5]. Research has shown that multijunction cells show increased tendency to degrade after exposure to reverse currents [see Yoo and lies, “Effects of Reverse Bias on Multijunction Cells”, 26th IEEE Photovoltaic Specialists Conference, 1997, p883–6]. The adoption of bypass diodes and reverse bias screening has become industry practice, and has led to satisfactory solar array performance.
Another problem with solar cell arrays is due to electrostatic discharge (ESD). Previously recognized ESD problems with solar cells involved the short circuiting of high voltage cellular arrays from high-energy electrostatic sustained vacuum arcs, powered by the energy output of the array, and triggered by differential charging of array dielectrics and structures. The short circuiting results from the electrical failure of the insulation materials between the solar cells and the conductive mechanical support structure. The results of this type of high-energy ESD are large sudden power losses caused by a permanent shunt.
Recently, another ESD problem has been discovered. Rather than large and sudden power losses occurring from high-energy ESD-initiated sustained vacuum arcs, gradual power losses resulting from moderate-energy ESD have been realized. The moderate-energy ESD causes large transient currents to flow through the cell array, which can cause large reverse currents and voltages to occur. Even with bypass diode protection, the transient reverse bias conditions can produce cellular level degradation of the cells. The repeated exposure to ESD slowly reduces the power output of the cells. A particular area of concern for moderate-energy ESD has been with multi-junction cells, such as GaAs, because of their greater sensitivity to reverse bias operation. Testing of multi-junction cells has shown that, as a result of ESD, a damaged multi-junction cell exhibits a lower maximum power and a degradation in fill factor. Fill factor degradation is typically caused by shunting across one of the junctions.
FIG. 1 is a diagram illustrating a prior art solar cell array 101. The solar cell array 101 comprises string series 102 of cells and serpentine series of cells 104, 106. The string series 102 of cells comprises a series of cells lined up in a single row. The negative terminals 102b of the string series may have a common negative terminal 105, while the positive terminals 102a of the string series may have a common positive terminal 103, or may be isolated by blocking diodes (not shown). The serpentine sections 104 and 106 are a series of solar cells that are connected in an S-like pattern. At the turns of the serpentine sections, a positive end 104b of one cell on one row is coupled to the negative end 104a of a cell on another row. Prior art arrays combine string series and serpentine series of cells to maximize the fraction of the array surface covered with solar cells.
FIG. 2 is a circuit diagram representing an ESD pulse 12 relative to a prior art solar cell 10. The ESD pulse 12 is represented as a current source having a current value IESD 14. The pulse current source 12 has positive 12a and negative 12b terminals. Typically, the ESD pulse current, IESD 14, may be 10's to 100's of amperes, and the duration of the ESD pulse may be microseconds to milliseconds. The solar cell 10 is part of a series of cells 17, and is also coupled to a load 100 and a ground 200. The solar cell 10 has positive 10a and negative 10b terminals. During normal operation, the series of cells may carry a cell current 15 from the cell 10 along current path 14b to the load 100, on the order of approximately 1 ampere, and each cell 10, 17 may generate a voltage, Vcell 19 of approximately 2 volts.
Damage occurs to a solar cell 10 when the ESD current 14 exceeds the cell current 15 and flows in the opposite direction 14a. The ESD pulse 12 impacts the solar cell 10 when the switch 16 is closed, causing the ESD pulse 12 to generate reverse current 14 through current path 14a. The large reverse current 14 through the cell 10, reverses the polarity of the cell 10, so that V18 18 is greater than Vcell 19. The large transient reverse current 14 can degrade and permanently damage the solar cell 10 similarly to the long duration reverse bias operation of shadowed or cracked cells.
Protection from these reverse bias conditions in prior art solar cell arrays has been achieved through the use of bypass diodes 30. These diodes 30 do not carry current under normal conditions when the cell voltage Vcell 19, is greater than V18 18. When the cell 10 voltage is reversed, the bypass diodes 30 conduct most of the reverse current, 14c, which would otherwise damage the solar cell 10. But these diodes 30 are designed for the small steady-state current (less than 1 amp) of the solar cell string. Recent testing of solar cells with bypass diodes has shown that the large and fast transient ESD current pulse 12 results in a large reverse voltage and current 14 sufficient to damage some solar cells 10 at the cellular level. Damage occurs, in part, due to the slow response time of the bypass diode 30, which allows a fast ESD current pulse 14 to produce a large reverse voltage and current 14 overshoot across the solar cell 10. Damage also occurs because the reverse voltage and current 14 remaining after the bypass diode 30 has responded is still above the reverse current 14 level used to screen out solar cells 10 that are susceptible to reverse bias degradation.
As can be seen, there is a need for measures to reduce or prevent cellular level ESD. Over time, a cell can degrade to such a degree that it will no longer provide a sufficient amount of power. Moreover, the measures should work for various solar cell series circuits, such as serpentine and string configurations.